The breakdown voltage of a semiconductor device is affected by the forbidden energy band gap width (energy band gap), critical breakdown field, and depletion layer width of the semiconductor serving as the material. The wider the band gap width and the higher the critical breakdown field of the semiconductor employed as the material, the greater the breakdown voltage of the semiconductor device obtained. Further, even for an identical critical breakdown field, the greater the depletion layer width formed in the active region, the greater the breakdown voltage. Since the width of the depletion layer is inversely proportional to the square root of the concentration of impurities such as donors and acceptors that are added to the active region, impurities have been added to adjust the breakdown voltage (see Japanese Unexamined Patent Publication (KOKAI) No. 2002-57109). Usually, in semiconductor devices requiring an increased breakdown voltage, the concentration of impurities added to the active region is reduced.
However, since the resistivity of a semiconductor is inversely proportional to the concentration of impurities, the higher the breakdown voltage of a semiconductor device, the greater the tendency for the resistance (specific on resistance) within the device in an ON state to be higher. An increase in ON resistance causes increase in power loss and corresponding heat generation. Accordingly, reducing the power loss within a device while increasing the breakdown voltage requires the use of a semiconductor substrate with a wide band gap and a high critical breakdown field. Thus, instead of silicon (Si) that is widely employed as a semiconductor substrate, the use of semiconductor materials with wide band gaps, such as silicon carbide (SiC) and gallium nitride (GaN), as materials of power semiconductor devices has begun.
As mentioned above, the wider the band gap of a semiconductor device, the greater the advantage afforded in increasing the breakdown voltage and reducing specific on resistance. Conversely, widening of the band gap width makes it hard to achieve a ohmic contact electrode (ohmic electrode) and reduce contact resistance. For example, in a Schottky barrier diode (SBD), a low concentration of impurity is added in the vicinity of the Schottky contact to widen the depletion layer, and a high concentration of impurity is added in the vicinity of the ohmic contact to reduce the contact resistance. In principle, the thickness of the semiconductor device should just be about the width of the depletion layer that can be ensure the desired resistant voltage, and is generally 10 μm or less. However, since it is necessary to increase mechanical strength, a low concentration layer of about 10 μm is formed on the low resistance substrate of several hundred microns, and a Schottky contact is formed on the surface thereof. Accordingly, when manufacturing power semiconductor devices with high uniformity and controllability, the concentration and thickness uniformity of the low concentration layer formed on the substrate are important. Further, in order to reduce specific on resistance as low as possible, it is necessary to increase the doping concentration of the substrate as high as possible.
In order to obtain an active layer with a high breakdown voltage, it is necessary to form a homoepitaxial layer with high resistivity. However, when anti-phase boundaries, stacking faults, and small-angle grain boundaries are present in this epitaxial layer, they act as a source of electrons and holes, making it difficult to achieve a prescribed breakdown voltage. Thus, the ELO method, undulation method, and the like are employed to reduce defects (see Japanese Unexamined Patent Publication (KOKAI) No. 2000-178740). However, even when employing one of the above-mentioned methods, it is necessary to process the substrate surface prior to growing the epitaxial layer. Further, with the ELO method, planar defects end up remaining in merged regions between crystals, and current may leak out through the defects. Further, with the undulation method, since statistical symmetry of slope must be maintained during processing and the reduction in crystalline defects is inversely proportional to the film thickness, complete elimination of planar defects is impossible.
Accordingly, it is an object of the present invention to provide a semiconductor and semiconductor substrate exhibiting low resistivity on the substrate side while exhibiting high resistivity in an epitaxially grown layer formed thereover; a method of manufacturing the same; and a semiconductor device employing this semiconductor.